Work with cross functional teams to optimize various parts of the SW stack AI Compiler, AI frameworks, device drivers, and firmware. Work on block & system level performance analysis for VLIW based AI Engine processor architecture. Bring up emerging ML models based on CNN, transformers and characterize performance. Develop and validate VLIW based processor systems on both

We are looking for a Systems Design Engineer to join the System level Test team in San Jose. You will be involved in the silicon life cycle from testing of emulated next generation RTL through to silicon validation. You will have a view of the full system but also will become an expert in certain IP down to the register level. We are looking for someone who can span the r

Defining programming and system interfaces to leverage the performance of AIE accelerators in a portable and scalable way Implementing efficient programming abstractions for ML, signal processing and HPC applications Applying strong software engineering skills to enable the implementation of key application use cases on the next generation architectures Functional/perform

Collaborate with architects, hardware engineers, and firmware engineers to understand the impact of new features on perf & power Analyze design metrics and make implementation choices to optimize PPA Build Power test plan documentation covering all critical design features Develop & execute Power vectors & generate high quality Power data Find CAC optimization opportuniti

Runtime Wrapper Development Design and implement C++ runtime wrappers , APIs, and frameworks for ML model execution. Collaborate with kernel developers to integrate ML operators seamlessly into high level ML frameworks like ONNX . Model Loading and Inference Interface with ONNX / Pytorch runtime engines to deploy the model on CPUs. Develop efficient model loading mechanis

Kernel Development Design and implement highly optimized C++ kernel library for Generative AI models . Collaborate with the research and software teams to integrate these kernels into our existing software stack. Vector Processor Optimization Work closely with hardware engineers to understand the architecture of VLIW vector core units such as MAC , GeMM, and non linear fu

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Implement and improve passes in the compiler Integrate compiler and compiled model with ML Frameworks (such as PyTorch and Tensorflow) Implement model partitioning in ML Frameworks and/or MLIR Implement runtime to distribute work to and collect results from x86 cores and the array of AIE cores Mentor and provide guidance to others Learn latest industry trends and bring ne

Manage technical interaction with OEM/ODM Partners to enable deployment of AMD Instinct Accelerators in Partner systems. Support Partners in the bring up and validation of AMD Instinct GPUs in their system, guide partners on use of AMD tools, qualification test methods, and analysis of test results. Lead the debug of Partner/Customer issues (HW, firmware, driver), working

Performance modeling and analysis of ML training and inference workloads across a single and multiple accelerators. In addition of exploring various tradeoff and design decision. Participate in hardware software co design for future hardware optimization on various ML workloads. Communicate and present the results of the performance analysis and modeling to customers, sta

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL an

This individual will be responsible for participating and driving large design blocks from early design stage to tapeout. Work responsibilities include synthesizing extremely high speed designs, following through with Place and Route and analyzing design results, and making changes to the RTL code as needed. Work involves daily interaction with other physical designers as

Develop new flow features around new EDA tools and tool capabilities Conduct evaluations of tool quality, tune the flow to get optimal results from existing tools and support the physical verification flow Deploy flows to design teams, work with design teams to help them take full advantage of the flow PREFERRED EXPERIENCE Expert knowledge of at least one EDA Physical ver

Perform data mining and statistical data analysis on wafer sort and final test parametrics to support initial product assessment Work closely with Tools Development engineers to feedback binning, yield and parametric results to enhance various Tools' capabilities and functions Develop methodologies to automate analytical tasks using scripting languages Qualifications BS o

Develop impactful marketing communications plans to ensure successful product launches and strong competitive product positioning in the market. Lead end to end campaign development for priority initiatives, crafting strategies that align with business objectives. Define requirements for strategic developer and customer enablement content. Create compelling marketing coll